Picture resolution enhancement with dithering and dedithering

ABSTRACT

A dithering technique in accordance with an inventive arrangement saves two bits per sample in a wideband video signal. In accordance with this arrangement, a dither signal is added to an n-bit video signal. The adder should include a limiter to avoid overflows. The samples are truncated after the addition. In truncation, the least significant two bits are simply discarded. Usually, dither values are small positive integers which tend to increase the DC content of the signal. A dither signal which can provide significant improvement in a subsampled signal is a two frequency dither in which the higher frequency has the higher amplitude. The dither signal can have any repetitive sequence of the numbers 0, 1, 2, 3 in any order within said sequence, for example, 0, 2, 1, 3, 0, 2, 1, 3, . . . , etc. The quarter-frequency component is usually more objectionable than the half-frequency component, even though the quarter-frequency component has half the amplitude of the half-frequency component. Accordingly, a dedithering scheme can be chosen to suppress only the quarter-frequency component. A first signal path of the dedithering circuit is for delay and amplitude matching. A second signal path includes a combination inverted bandpass filter and limiter. The inverted bandpass filter cancels the frequency at the center of the passband when added to the delay and amplitude matched original signal. The limiter assures that only amplitudes of dither size will be cancelled.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the field of televisions capable of displayingside by side pictures of substantially equal size and comparable picturequality from different sources, and in particular, to such televisionshaving a wide display format ratio screen. Most televisions today have aformat display ratio, horizontal width to vertical height, of 4:3. Awide format display ratio corresponds more closely to the display formatratio of movies, for example 16:9. The invention is applicable to bothdirect view televisions and projection televisions.

2. Description of Related Art

Televisions having a format display ratio of 4:3, often referred to as4×3, are limited in the ways that single and multiple video signalsources can be displayed. Television signal transmissions of commercialbroadcasters, except for experimental material, are broadcast with a 4×3format display ratio. Many viewers find the 4×3 display format lesspleasing than the wider format display ratio associated with the movies.Televisions with a wide format display ratio provide not only a morepleasing display, but are capable of displaying wide display formatsignal sources in a corresponding wide display format. Movies "look"like movies, not cropped or distorted versions thereof. The video sourceneed not be cropped, either when converted from film to video, forexample with a telecine device, or by processors in the television.

Televisions with a wide display format ratio are also suited to a widevariety of displays for both conventional and wide display formatsignals, as well as combinations thereof in multiple picture displays.However, the use of a wide display ratio screen entails numerousproblems. Changing the display format ratios of multiple signal sources,developing consistent timing signals from asynchronous butsimultaneously displayed sources, switching between multiple sources togenerate multiple picture displays, and providing high resolutionpictures from compressed data signals are general categories of suchproblems. A wide screen television according to various inventivearrangements is capable of providing high resolution, single andmultiple picture displays, from single and multiple sources havingsimilar or different format ratios, and with selectable display formatratios. This invention is directed in particular to providing highresolution pictures from compressed data signals.

Television apparatus with conventional format display ratios can beequipped for displaying multiple pictures, for example from two videosources. The video sources may be the tuner in the television, a tunerin a video cassette recorder, a video camera, and others. In a modeoften referred to as picture-in-picture (PIP), the tuner in thetelevision provides a picture filling most of the screen, or displayarea, and an auxiliary video source provides a small inset picturegenerally within the boundaries of the larger picture. A PIP displaymode in a wide screen television apparatus is shown in FIG. 1(c). Inmany instances, the inset picture can be positioned in a number ofdifferent locations. Another display mode is often referred to aschannel scan, wherein a large number of small pictures, each from adifferent channel source, fill the screen in a freeze frame montage.There is no main picture, at least in terms of size. A channel scandisplay mode in a wide screen television apparatus is shown in FIG.1(i). In wide screen television apparatus, other display modes arepossible. One is referred to as picture-outside-picture (POP). In thismode, several inset auxiliary pictures can share a common boundary witha main picture. A POP display mode in a wide screen television apparatusis shown in FIG. 1(f). another mode particularly suited for a widescreen television is side by side pictures of substantially the samesize, from different video sources, for example two different channels.This mode is illustrated for a wide screen television in FIG. 1(d) fortwo 4:3 video sources. It will be appreciated that this mode can beconsidered a special case of the POP mode.

The synchronization of asynchronous video signals often requires thatsuccessive fields of one of the signals be stored in one or more fieldmemories. Limitations on memory space can impose a need to compress thedata of the stored signal to enable storage in limited capacity fieldmemories, or a need to sample the data at a lower sampling rate than theother video signal. This can result in lower quantization resolution forthe stored video signal when the pictures are displayed, particularly ifthe stored picture is larger than a typically small PIP or POP. In theside by side picture mode described above, where the main and auxiliaryvideo signals are displayed side by side, and with equal size, a lowerquantization resolution in the auxiliary picture can be apparent fromeven a casual comparison of the two pictures. It would be desirable forpictures from different video sources to be displayed side by side, forexample on a wide screen television, with substantially comparablepicture quality, even when one of the signals has a lower quantizationresolution.

SUMMARY OF THE INVENTION

In accordance with inventive arrangements, one of a plurality ofresolution enhancing schemes may be selected for optimum picture qualityunder different circumstances. These schemes include dithering,dithering and dedithering, skewing of dither sequences and paired pixelreplacement and reconstruction. Dithering techniques for saving bits indigital video signals have been described, for example in U.S. Pat. No.4,594,726 - Willis. Usually, these schemes try to save one bit persample in a wideband signal or several bits per sample in a narrow bandsignal which is carried in a wideband video signal.

A dithering technique in accordance with an inventive arrangement savestwo bits per sample in a wideband video signal. In accordance with thisarrangement, a dither signal is added to an n-bit video signal. Theadder should include a limiter to avoid overflows. The samples aretruncated after the addition. In truncation, the least significant twobits are simply discarded. Usually, dither values are small positiveintegers which tend to increase the DC content of the signal. Truncationtends to decrease the DC content, and indeed, the dither signal isusually developed to cancel the increase with the decrease. A dithersignal which can provide significant improvement in a subsampled signalis a two frequency dither in which the higher frequency has the higheramplitude. In accordance with an inventive arrangement, the dithersignal can be defined by any repetitive sequence of the numbers 0, 1, 2,3 in any order within the sequence. One such dither sequence is:

    0, 2, 1, 3, 0, 2, 1, 3, . . . , etc.

This dither sequence is the sum of two other sequence, namely:

    0, 2, 0, 2, 0, 2, 0, 2, . . . , etc.; and,

    0, 0, 1, 1, 0, 0, 1, 1, . . . , etc.

The choice of dithering with 0, 2, 1, 3, 0, 2, 1, 3, . . . , etc., forexample, is based on the conclusion that a higher frequency dither isless noticeable than a lower frequency dither.

It appears that the quarter-frequency component is usually moreobjectionable than the half-frequency component, even though thequarter-frequency component has half the amplitude of the half-frequencycomponent. Accordingly, a dedithering scheme can be chosen to suppressonly the quarter-frequency component. A first signal path of thededithering circuit is for delay and amplitude matching. A second signalpath includes a combination inverted bandpass filter and limiter. Theinverted bandpass filter cancels the frequency at the center of thepassband when added to the delay and amplitude matched original signal.The limiter assures that only amplitudes of dither size will becancelled. This dedithering arrangement has no effect upon the halfsample frequency component of the dithered signal. The half-frequencysignal component is low enough in amplitude and high enough infrequency, for example, at the Nyquist limit of the signal, to havesufficiently low visibility to avoid causing a problem.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS 1(a)-1i) are useful for explaining different display formats of awide screen television.

FIG. 2 is a block diagram of a wide screen television in accordance withaspects of this invention and adapted for operation at 2 f_(H)horizontal scanning.

FIG. 3 is a block diagram of the wide screen processor shown in FIG. 2.

FIG. 4 is a block diagram showing further details of the wide screenprocessor shown in FIG. 3.

FIG. 5 is a block diagram of the picture-in-picture processor shown inFIG. 4.

FIG. 6 is a block diagram of the gate array shown in FIG. 4,illustrating the main, auxiliary and output signal paths.

FIGS. 7 and 8 are timing diagrams useful for explaining the generationof the display format shown in FIG. 1(d), using fully cropped signals.

FIG. 9 is a block diagram showing the main signal path of FIG. 6 in moredetail.

FIG. 10 is a block diagram showing the auxiliary signal path of FIG. 6in more detail.

FIG. 11 is a block diagram of the the timing and control section of thepicture-in-picture processor of FIG. 5.

FIG. 12 is a block diagram of a circuit for generating the internal 2f_(H) signal in the 1 f_(H) to 2 f_(H) conversion.

FIG. 13 is a combination block and circuit diagram for the deflectioncircuit shown in FIG. 2.

FIG. 14 is a block diagram of the RGB interface shown in FIG. 2.

FIGS. 15 and 16 are block diagrams for 1-bit dithering and deditheringcircuits respectively, for implementing the resolution processingcircuits of FIG. 4 and FIG. 10.

FIGS. 17 and 18 are a block diagrams for 2-bit dithering and deditheringcircuits respectively, for implementing the resolution processingcircuits of FIG. 4 and FIG. 10.

FIG. 19 is a table useful for explaining a skewing scheme for enhancingoperation of the circuits shown in FIGS. 15-18.

FIG. 20 is a table useful for explaining yet another alternative forimplementing the resolution processing circuits of FIG. 4 and FIG. 10.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The various parts of FIG. 1 illustrate some, but not all of the variouscombinations of single and multiple picture display formats which can beimplemented according to different inventive arrangements. Thoseselected for illustration are intended to facilitate the description ofparticular circuits comprising wide screen televisions according to theinventive arrangements. For purposes of convenience in illustration anddiscussion herein, a conventional display format ratio of width toheight for a video source or signal is generally deemed to be 4×3,whereas a wide screen display format ratio of width to height for avideo source or signal is generally deemed to be 16×9. The inventivearrangements are not limited by these definitions.

FIG. 1(a) illustrates a television, direct view or projection, having aconventional format display ratio of 4×3. When a 16×9 format displayratio picture is transmitted, as a 4×3 format display ratio signal,black bars appear at the top and at the bottom. This is commonlyreferred to as letterbox format. In this instance, the viewed picture israther small with respect to the entire available display area.Alternatively, the 16×9 format display ratio source is converted priorto transmission, so that it will fill the vertical extent of a viewingsurface of 4×3 format display. However, much information will be croppedfrom the left and/or right sides. As a further alternative, theletterbox picture can be expanded vertically but not horizontally,whereby the resulting picture will evidence distortion by verticalelongation. None of the three alternatives is particularly appealing.

FIG. 1(b) shows a 16×9 screen. A 16×9 format display ratio video sourcewould be fully displayed, without cropping and without distortion. A16×9 format display ratio letterbox picture, which is itself in a 4×3format display ratio signal, can be progressively scanned by linedoubling or line addition, so as to provide a larger display withsufficient vertical resolution. A wide screen television in accordancewith this invention can display such a 16×9 format display ratio signalwhether the main source, the auxiliary source or an external RGB source.

FIG. 1(c) illustrates a 16×9 format display ratio main signal in which a4×3 format display ratio inset picture is displayed. If both the mainand auxiliary video signals are 16×9 format display ratio sources, theinset picture can also have a 16×9 format display ratio. The insetpicture can be displayed in many different positions.

FIG. 1(d) illustrates a display format, wherein the main and auxiliaryvideo signals are displayed with the same size picture. Each displayarea has an format display ratio of 8×9, which is of course differentfrom both 16×9 and 4×3. In order to show a 4×3 format display ratiosource in such a display area, without horizontal or verticaldistortion, the signal must be cropped on the left and/or right sides.More of the picture can be shown, with less cropping, if some aspectratio distortion by horizontal squeezing of the picture is tolerated.Horizontal squeezing results in vertical elongation of objects in thepicture. The wide screen television according to this invention canprovide any mix of cropping and aspect ratio distortion from maximumcropping with no aspect ratio distortion to no cropping with maximumaspect ratio distortion.

Data sampling limitations in the auxiliary video signal processing pathcomplicate the generation of a high resolution picture which is as largein size as the display from the main video signal. Various methods canbe developed for overcoming these complications.

FIG. 1(e) is a display format wherein a 4×3 format display ratio pictureis displayed in the center of a 16×9 format display ratio screen. Darkbars are evident on the right and left sides.

FIG. 1(f) illustrates a display format wherein one large 4×3 formatdisplay ratio picture and three smaller 4×3 format display ratiopictures are displayed simultaneously. A smaller picture outside theperimeter of the large picture is sometimes referred to as a POP, thatis a picture-outside-picture, rather than a PIP, a picture-in-picture.The terms PIP or picture-in-picture are used herein for both displayformats. In those circumstances where the wide screen television isprovided with two tuners, either both internal or one internal and oneexternal, for example in a video cassette recorder, two of the displayedpictures can display movement in real time in accordance with thesource. The remaining pictures can be displayed in freeze frame format.It will be appreciated that the addition of further tuners andadditional auxiliary signal processing paths can provide for more thantwo moving pictures. It will also be appreciated that the large pictureon the one hand, and the three small pictures on the other hand, can beswitched in position, as shown in FIG. 1(g).

FIG. 1(h) illustrates an alternative wherein the 4×3 format displayratio picture is centered, and six smaller 4×3 format display ratiopictures are displayed in vertical columns on either side. As in thepreviously described format, a wide screen television provided with twotuners can provide two moving pictures. The remaining eleven pictureswill be in freeze frame format.

FIG. 1(i) shows a display format having a grid of twelve 4×3 formatdisplay ratio pictures. Such a display format is particularlyappropriate for a channel selection guide, wherein each picture is atleast a freeze frame from a different channel. As before, the number ofmoving pictures will depend upon the number of available tuners andsignal processing paths.

The various formats shown in FIG. 1 are illustrative, and not limiting,and can be implemented by wide screen televisions shown in the remainingdrawings and described in detail below.

An overall block diagram for a wide screen television in accordance withinventive arrangements, and adapted to operate with 2 f_(H) horizontalscanning, is shown in FIG. 2 and generally designated 10. The television10 generally comprises a video signals input section 20, a chassis or TVmicroprocessor 216, a wide screen processor 30, a 1 f_(H) to 2 f_(H)converter 40, a deflection circuit 50, an RGB interface 60, a YUV to RGBconverter 240, kine drivers 242, direct view or projection tubes 244 anda power supply 70. The grouping of various circuits into differentfunctional blocks is made for purposes of convenience in description,and is not intended as limiting the physical position of such circuitsrelative to one another.

The video signals input section 20 is adapted for receiving a pluralityof composite video signals from different video sources. The videosignals may be selectively switched for display as main and auxiliaryvideo signals. An RF switch 204 has two antenna inputs ANT1 and ANT 2.These represent inputs for both off-air antenna reception and cablereception. The RF switch 204 controls which antenna input is supplied toa first tuner 206 and to a second tuner 208. The output of first tuner206 is an input to a one-chip 202, which performs a number of functionsrelated to tuning, horizontal and vertical deflection and videocontrols. The particular one-chip shown in industry designated typeTA7730. The baseband video signal VIDEO OUT developed in the one-chipand resulting from the signal from first tuner 206 is an input to bothvideo switch 200 and the TV1 input of wide screen processor 30. Otherbaseband video inputs to video switch 200 are designated AUX1 and AUX 2.These might be used for video cameras, laser disc players, video tapeplayers, video games and the like. The output of the video switch 200,which is controlled by the chassis or TV microprocessor 216 isdesignated SWITCHED VIDEO. The SWITCHED VIDEO is another input to widescreen processor 30.

With further reference to FIG. 3, a switch SW1 wide screen processorselects between the TV1 and SWITCHED VIDEO signals as a SEL COMP OUTvideo signal which is an input to a Y/C decoder 210. The Y/C decoder 210may be implemented as an adaptive line comb filter. Two further videosources S1 and S2 are also inputs to the Y/C decoder 210. Each of S1 andS2 represent different S-VHS sources, and each consists of separateluminance and chrominance signals. A switch, which may be incorporatedas part of the Y/C decoder, as in some adaptive line comb filters, orwhich may be implemented as a separate switch, is responsive to the TVmicroprocessor 216 for selecting one pair of luminance and chrominancesignals as outputs designated Y₁₃ M and C₁₃ IN respectively. Theselected pair of luminance and chrominance signals is thereafterconsidered the main signal and is processed along a main signal path.Signal designations including ₁₃ M or ₋₋ MN refer to the main signalpath. The chrominance signal C₁₃ IN is redirected by the wide screenprocessor back to the one-chip, for developing color difference signalsU₁₃ M and V₁₃ M. In this regard, U is an equivalent designation for(R-Y) and V is an equivalent designation for (B-Y). The Y₋₋ M, U₋₋ M,and V₋₋ M signals are converted to digital form in the wide screenprocessor for further signal processing.

The second tuner 208, functionally defined as part of the wide screenprocessor 30, develops a baseband video signal TV2. A switch SW2 selectsbetween the TV2 and SWITCHED VIDEO signals as an input to a Y/C decoder220. The Y/C decoder 220 may be implemented as an adaptive line combfilter. Switches SW3 and SW4 select between the luminance andchrominance outputs of Y/C decoder 220 and the luminance and chrominancesignals of an external video source, designated Y₋₋ EXT and C₋₋ EXTrespectively. The Y₋₋ EXT and C₋₋ EXT signals correspond to the S-VHSinput S1. The Y/C decoder 220 and switches SW3 and SW4 may be combined,as in some adaptive line comb filters. The output of switches SW3 andSW4 is thereafter considered the auxiliary signal and is processed alongan auxiliary signal path. The selected luminance output is designatedY₋₋ A. Signal designations including ₋₋ A, ₋₋ AX and ₋₋ AUX refer to theauxiliary signal path. The selected chrominance is converted to colordifference signals U₋₋ A and V₋₋ A. The Y₋₋ A, U₋₋ A and V₋₋ A signalsare converted to digital form for further signal processing. Thearrangement of video signal source switching in the main and auxiliarysignal paths maximizes flexibility in managing the source selection forthe different parts of the different picture display formats.

A composite synchronizing signal COMP SYNC, corresponding to Y₋₋ M isprovided by the wide screen processor to a sync separator 212. Thehorizontal and vertical synchronizing components H and V respectivelyare inputs to a vertical countdown circuit 214. The vertical countdowncircuit develops a VERTICAL RESET signal which is directed into the widescreen processor 30. The wide screen processor generates an internalvertical reset output signal INT VERT RST OUT directed to the RGBinterface 60. A switch in the RGB interface 60 selects between theinternal vertical reset output signal and the vertical synchronizingcomponent of the external RGB source. The output of this switch is aselected vertical synchronizing component SEL₋₋ VERT₋₋ SYNC directed tothe deflection circuit 50. Horizontal and vertical synchronizing signalsof the auxiliary video signal are developed by sync separator 250 in thewide screen processor.

The 1 f_(H) to 2 f_(H) converter 40 is responsible for convertinginterlaced video signals to progressively scanned noninterlaced signals,for example one wherein each horizontal line is displayed twice, or anadditional set of horizontal lines is generated by interpolatingadjacent horizontal lines of the same field. In some instances, the useof a previous line or the use of an interpolated line will depend uponthe level of movement which is detected between adjacent fields orframes. The converter circuit 40 operates in conjunction with a videoRAM 420. The video RAM may be used to store one or more fields of aframe, to enable the progressive display. The converted video data asY₋₋ 2 f_(H), U₋₋ 2 f_(H) and V₋₋ 2 f_(H) signals is supplied to the RGBinterface 60.

The RGB interface 60, shown in more detail in FIG. 14, enables selectionof the converted video data or external RGB video data for display bythe video signals input section. The external RGB signal is deemed to bea wide format display ratio signal adapted for 2 f_(H) scanning. Thevertical synchronizing component of the main signal is supplied to theRGB interface by the wide screen processor as INT VERT RST OUT, enablinga selected vertical sync (f_(Vm) or f_(Vext)) to be available to thedeflection circuit 50. Operation of the wide screen television enablesuser selection of an external RGB signal, by generating aninternal/external control signal INT/EXT. However, the selection of anexternal RGB signal input, in the absence of such a signal, can resultin vertical collapse of the raster, and damage to the cathode ray tubeor projection tubes. Accordingly, the RGB interface circuit detects anexternal synchronizing signal, in order to override the selection of anon-existent external RGB input. The WSP microprocessor 340 alsosupplies color and tint controls for the external RGB signal.

The wide screen processor 30 comprises a picture in picture processor320 for special signal processing of the auxiliary video signal. Theterm picture-in-picture is sometimes abbreviated as PIP or pix-in-pix. Agate array 300 combines the main and auxiliary video signal data in awide variety of display formats, as shown by the examples of FIGS. 1(b)through 1(i). The picture-in-picture processor 320 and gate array 300are under the control of a wide screen microprocessor (WSP μP) 340.Microprocessor 340 is responsive to the TV microprocessor 216 over aserial bus. The serial bus includes four signal lines, for data, clocksignals, enable signals and reset signals. The wide screen processor 30also generates a composite vertical blanking/reset signal, as a threelevel sandcastle signal. Alternatively, the vertical blanking and resetsignals can be generated as separate signals. A composite blankingsignal is supplied by the video signal input section to the RGBinterface.

The deflection circuit 50, shown in more detail in FIG. 13, receives avertical reset signal from the wide screen processor, a selected 2 f_(H)horizontal synchronizing signal from the RGB interface 60 and additionalcontrol signals from the wide screen processor. These additional controlsignals relate to horizontal phasing, vertical size adjustment andeast-west pin adjustment. The deflection circuit 50 supplies 2 f_(H)flyback pulses to the wide screen processor 30, the 1 f_(H) to 2 f_(H)converter 40 and the YUV to RGB converter 240.

Operating voltages for the entire wide screen television are generatedby a power supply 70 which can be energized by an AC mains supply.

The wide screen processor 30 is shown in more detail in FIG. 3. Theprincipal components of the wide screen processor are a gate array 300,a picture-in-picture circuit 301, analog to digital and digital toanalog converters, the second tuner 208, a wide screen processormicroprocessor 340 and a wide screen output encoder 227. Further detailsof the wide screen processor, which are in common with both the 1 f_(H)and the 2 f_(H) chassis, for example the PIP circuit, are shown in FIG.4. A picture-in-picture processor 320, which forms a significant part ofthe PIP circuit 301, is shown in more detail in FIG. 5. The gate array300 is shown in more detail in FIG. 6. A number of the components shownin FIG. 3, forming parts of the main and auxiliary signal paths, havealready been described in detail.

The second tuner 208 has associated therewith an IF stage 224 and anaudio stage 226. The second tuner 208 also operates in conjunction withthe WSP μP 340. The WSP μP 340 comprises an input output I/O section340A and an analog output section 340B. The I/O section 340A providestint and color control signals, the INT/EXT signal for selecting theexternal RGB video source and control signals for the switches SW1through SW6. The I/O section also monitors the EXT SYNC DET signal fromthe RGB interface to protect the deflection circuit and cathode raytube(s). The analog output section 340B provides control signals forvertical size, east-west adjust and horizontal phase, through respectiveinterface circuits 254, 256 and 258.

The gate array 300 is responsible for combining video information fromthe main and auxiliary signal paths to implement a composite wide screendisplay, for example one of those shown in the different parts ofFIG. 1. Clock information for the gate array is provided by phase lockedloop 374, which operates in conjunction with low pass filter 376. Themain video signal is supplied to the wide screen processor in analogform, and Y U V format, as signals designated Y₋₋ M, U₋₋ M and V₋₋ M.These main signals are converted from analog to digital form by analogto digital converters 342 and 346, shown in more detail in FIG. 4.

The color component signals are referred to by the generic designationsU and V, which may be assigned to either R-Y or B-Y signals, or I and Qsignals. The sampled luminance bandwidth is limited to 8 MHz because thesystem clock rate is 1024 f_(H), which is approximately 16 MHz. A singleanalog to digital converter and an analog switch can be used to samplethe color component data because the U and V signals are limited to 500KHz, or 1.5 MHz for wide I. The select line UV₋₋ MUX for the analogswitch, or multiplexer 344, is an 8 MHz signal derived by dividing thesystem clock by 2. A one clock wide start of line SOL pulsesynchronously resets this signal to zero at the beginning of eachhorizontal video line. The UV₋₋ MUX line than toggles in state eachclock cycle through the horizontal line. Since the line length is aneven number of clock cycles, the state of the UV₋₋ MUX, onceinitialized, will consistently toggle 0, 1, 0, 1 , . . . , withoutinterruption. The Y and UV data streams out of the analog to digitalconverters 342 and 346 are shifted because the analog to digitalconverters each have 1 clock cycle of delay. In order to accommodate forthis data shift, the clock gating information from the interpolatorcontrol 349 of main signal processing path 304 must be similarlydelayed. Were the clock gating information not delayed, the UV data willnot be correctly paired when deleted. This is important because each UVpair represents one vector. A U element from one vector cannot be pairedwith a V element from another vector without causing a color shift.Instead, a V sample from a previous pair will be deleted along with thecurrent U sample. This method of UV multiplexing is referred to as2:1:1, as there are two luminance samples for every pair of colorcomponent (U, V) samples. The Nyquist frequency for both U and V iseffectively reduced to one half of the luminance Nyquist frequency.Accordingly, the Nyquist frequency of the output of the analog todigital converter for the luminance component is 8 MHz, whereas theNyquist frequency of the output of the analog to digital converter forthe color components is 4 MHz.

The PIP circuit and/or the gate array may also include means forenhancing the resolution of the auxiliary data notwithstanding the datacompression. A number of data reduction and data restoration schemeshave been developed, including for example paired pixel compression anddithering and dedithering. Moreover, different dithering sequencesinvolving different numbers of bits and different paired pixelcompressions involving different numbers of bits are contemplated. Oneof a number of particular data reduction and restoration schemes can beselected by the WSP μP 340 in order to maximize resolution of thedisplayed video for each particular kind of picture display format.These schemes are explained in detail in connection with FIGS. 15-20.

The gate array includes interpolators which operate in conjunction withline memories, which may be implemented as FIFO's 356 and 358. Theinterpolator and FIFO's are utilized to resample the main signal asdesired. An additional interpolator can resample the auxiliary signal.Clock and synchronizing circuits in the gate array control the datamanipulation of both the main and auxiliary signals, including thecombination thereof into a single output video signal having Y₋₋ MX, U₋₋MX and V₋₋ MX components. These output components are converted toanalog form by digital to analog converters 360, 362 and 364. The analogform signals, designated Y, U and V, are supplied to the 1 f_(H) to 2f_(H) converter 40 for conversion to noninterlaced scanning. The Y, Uand V signals are also encoded to Y/C format by encoder 227 to define awide format ratio output signal Y₋₋ OUT₋₋ EXT/C₋₋ OUT₋₋ EXT available atpanel jacks. Switch SWS selects a synchronizing signal for the encoder227 from either the gate array, C₋₋ SYNC₋₋ MN, or from the PIP circuit,C₋₋ SYNC₋₋ AUX. Switch SW6 selects between Y₋₋ M and C₋₋ SYNC₋₋ AUX assynchronizing signal for the wide screen panel output.

Portions of the horizontal synchronizing circuit are shown in moredetail in FIG. 12. Phase comparator 228 is part of a phase locked loopincluding low pass filter 230, voltage controlled oscillator 232,divider 234 and capacitor 236. The voltage controlled oscillator 232operates at 32 f_(H), responsive to a ceramic resonator or the like 238.The output of the voltage controlled oscillator is divided by 32 toprovide a proper frequency second input signal to phase comparator 228.The output of the divider 234 is a 1 f_(H) REF timing signal. The 32f_(H) REF and 1 f_(H) REF timing signals are supplied to a divide by 16counter 400. A 2 f_(H) output is supplied to a pulse width circuit 402.Presetting divider 400 by the 1 f_(H) REF signal assures that thedivider operates synchronously with the phase locked loop of the videosignals input section. Pulse width circuit 402 assures that a 2 f_(H)-REF signal will have an adequate pulse width to assure proper operationof the phase comparator 404, for example a type CA1391, which forms partof a second phase locked loop including low pass filter 406 and 2 f_(H)voltage controlled oscillator 408. Voltage controlled oscillator 408generates an internal 2 f_(H) timing signal, which is used for drivingthe progressively scanned display. The other input signal to phasecomparator 404 is the 2 f_(H) flyback pulses or a timing signal relatedthereto. The use of the second phase locked loop including phasecomparator 404 is useful for assuring that each 2 f_(H) scanning periodis symmetric within each 1 f_(H) period of the input signal. Otherwise,the display may exhibit a raster split, for example, wherein half of thevideo lines are shifted to the right and half of the video lines areshifted to the left.

The deflection circuit 50 is shown in more detail in FIG. 13 A circuit500 is provided for adjusting the vertical size of the raster, inaccordance with a desired amount of vertical overscan necessary forimplementing different display formats. As illustrated diagrammatically,a constant current source 502 provides a constant quantity of currentI_(RAMP) which charges a vertical ramp capacitor 504. A transistor 506is coupled in parallel with the vertical ramp capacitor, andperiodically discharges the capacitor responsive to the vertical resetsignal. In the absence of any adjustment, current I_(RAMP) provides themaximum available vertical size for the raster. This might correspond tothe extent of vertical overscan needed to fill the wide screen displayby an expanded 4×3 format display ratio signal source, as shown in FIG.1(a). To the extent that less vertical raster size is required, anadjustable current source 508 diverts a variable amount of currentI_(ADJ) from I_(RAMP), so that vertical ramp capacitor 504 charges moreslowly and to a smaller peak value. Variable current source 508 isresponsive to a vertical size adjust signal, for example in analog form,generated by a vertical size control circuit. Vertical size adjustment500 is independent of a manual vertical size adjustment 510, which maybe implemented by a potentiometer or back panel adjustment knob. Ineither event, the vertical deflection coil(s) 512 receive(s) drivingcurrent of the proper magnitude. Horizontal deflection is provided byphase adjusting circuit 518, East-West pin correction circuit 514, a 2f_(H) phase locked loop 520 and horizontal output circuit 516.

The RGB interface circuit 60 is shown in more detailed in FIG. 14. Thesignal which is to be ultimately displayed will be selected between theoutput of the 1 f_(H) to 2 f_(H) converter 40 and an external RGB input.For purposes of the wide screen television described herein, theexternal RGB input presumed to be a wide format display ratio,progressively scanned source. The external RGB signals and a compositeblanking signal from the video signals input section 20 are inputs to anRGB to Y U V converter 610. The external 2 f_(H) composite synchronizingsignal for the external RGB signal is an input to external syncrhonizingsignal separator 600. Selection of the vertical synchronizing signal isimplemented by switch 608. Selection of the horizontal synchronizingsignal is implemented by switch 604. Selection of the video signal isimplemented by switch 606. Each of the switches 604, 606 and 608 isresponsive to an internal/external control signal generated by the WSPμP 340. Selection of internal or external video sources is a userselection. However, if a user inadvertently selects an external RGBsource, when no such source is connected or turned on, or if theexternal source drops out, the vertical raster will collapse, andserious damage to the cathode ray tube(s) can result. Accordingly, anexternal synchronizing detector 602 checks for the presence of anexternal synchronizing signal. In the absence of such a signal, a switchoverride control signal is transmitted to each of switches 604, 606 and608, to prevent selection of the external RGB source if the signaltherefrom is not present. The RGB to YUV converter 610 also receivestint and color control signals from the WSP μP 340.

A wide screen television in accordance with the inventive arrangementscan be implemented with 1 f_(H) horizontal scanning instead of 2 f_(H)horizontal scanning, although such a circuit is not illustrated. A 1f_(H) circuit would not require the 1 f_(H) to 2 f_(H) converter and theRGB interface. Accordingly, there would be no provision for displayingan external wide format display ratio RGB signal at a 2 f_(H) scanningrate. The wide screen processor and picture-in-picture processor for a 1f_(H) circuit would be very similar. The gate array could besubstantially identical, although not all of the inputs and outputswould be utilized. The various resolution enhancement schemes describedherein can be generally applied without regard to whether the televisionoperates with 1 f_(H) or 2 f_(H) scanning.

FIG. 4 is a block diagram showing further details of the wide screenprocessor 30 shown in FIG. 3 which would be the same for both a 1 f_(H)and 2 f_(H) chassis. The Y₋₋ A, U₋₋ A and V₋₋ A signals are an input tothe picture in picture processor 320, which can include a resolutionprocessing circuit 370. The wide screen television according to aspectsof this invention can expand and compress video. The special effectsembodied by the various composite display formats illustrated in part inFIG. 1 are generated by the picture-in-picture processor 320, which canreceive resolution processed data signals Y₋₋ RP, U₋₋ RP and V₋₋ RP fromresolution processing circuit 370. Resolution processing need not beutilized at all times, but during selected display formats. Thepicture-in-picture processor 320 is shown in more detail in FIG. 5. Theprincipal components of the picture-in-picture processor are ananalog-to-digital converter section 322, an input section 324, a fastswitch (FSW) and bus section 326, a timing and control section 328 and adigital-to-analog converter section 330. The timing and control section328 is shown in more detail in FIG. 11.

The picture-in-picture processor 320 may be embodied as an improvedvariation of a basic CPIP chip developed by Thomson ConsumerElectronics, Inc. The basic CPIP chip is described more fully in apublication entitled The CTC 140 Picture in Picture (CPIP) TechnicalTraining Manual, available from Thomson Consumer Electronics, Inc.,Indianapolis, Ind. A number of special features or special effects arepossible, the following being illustrative. The basic special effect isa large picture having a small picture overlaying a portion thereof asshown in FIG. 1(c). The large and small pictures can result from thesame video signal, from different video signals and can be interchangedor swapped. Generally speaking, the audio signal is switched to alwayscorrespond to the big picture. The small picture can be moved to anyposition on the screen or can step through a number of predeterminedpositions. A zoom feature increases and decreases the size of the smallpicture, for example to any one of a number of preset sizes. At somepoint, for example the display format shown in FIG. 1(d), the large andsmall pictures are in fact the same size.

In a single picture mode, for example that shown in FIGS. 1(b), 1(e) or1(f) a user can zoom in on the content of the single picture, forexample, in steps from a ratio of 1.0:1 to 5.0:1. While in the zoom modea user may search or pan through the picture content enabling the screenimage to move across different areas of the picture. In either event,either the small picture or the large picture or the zoomed picture canbe displayed in freeze frame (still picture format). This functionenables a strobe format, wherein the last nine frames of video can berepeated on the screen. The frame repetition rate can be changed fromthirty frames per second to zero frames per second.

The picture-in-picture processor used in the wide screen televisionaccording to another inventive arrangement differs from the presentconfiguration of the basic CPIP chip described above. If the basic CPIPchip were used with a television having 16×9 screen, and without a videospeed up circuit, the inset pictures would exhibit aspect ratiodistortion, due to the effective 4/3 times horizontal expansionresulting from scanning across the wider 16×9 screen. Objects in thepicture would be horizontally elongated. If an external speed up circuitwere utilized, there would be no aspect ratio distortion, but thepicture would not fill the entire screen.

Existing picture-in-picture processors based on the basic CPIP chip asused in conventional televisions are operated in a particular fashionhaving certain undesirable consequences. The incoming video is sampledwith a 640 f_(H) clock which is locked to the horizontal synchronizingsignal of the main video source. In other words, data stored in thevideo RAM associated with the CPIP chip is not orthogonally sampled withrespect to the incoming auxiliary video source. This is a fundamentallimitation on the basic CPIP method of field synchronization. Thenonorthogonal nature of the input sampling rate results in skew errorsof the sampled data. The limitation is a result of the video RAM usedwith the CPIP chip, which must use the same clock for writing andreading data. When data from the video RAM, such as video RAM 350, isdisplayed, the skew errors are seen as random jitter along verticaledges of the picture and are generally considered quite objectionable.

The picture-in-picture processor 320, according to an inventivearrangement and unlike the basic CPIP chip, is adapted forasymmetrically compressing the video data in one of a plurality ofselectable display modes. In this mode of operation, the pictures arecompressed 4:1 in the horizontal direction and 3:1 in the verticaldirection. This asymmetric mode of compression produces aspect ratiodistorted pictures for storage in the video RAM. Objects in the picturesare squeezed horizontally. However, if these pictures are read outnormally, as for example in the channel scan mode, for display of a 16×9format display ratio screen, the pictures appear correct. The picturefills the screen and there is no aspect ratio distortion. The asymmetriccompression mode according to this aspect of the invention makes itpossible to generate the special display formats on a 16×9 screenwithout external speed up circuitry.

FIG. 11 is a block diagram of the timing and control section 328 of thepicture-in-picture processor, for example a modified version of the CPIPchip described above, which includes a decimation circuit 328C forimplementing the asymmetric compression as one of a plurality ofselectable display modes. The remaining display modes can provideauxiliary pictures of different sizes. Each of horizontal and verticaldecimation circuits comprises a counter which is programmed for acompression factor from a table of values under the control of the WSPμP 340. The range of values can be 1:1, 2:1, 3:1 and so on. Thecompression factors can be symmetric or asymmetric, depending upon howthe table is set up. Control of the compression ratios can also beimplemented by fully programmable, general purpose decimation circuitsunder the control of the WSP μP 340.

In full screen PIP modes, the picture-in-picture processor, inconjunction with a free running oscillator 348 will take Y/C input froma decoder, for example an adaptive line comb filter, decode the signalinto Y, U, V color components and generate horizontal and vertical syncpulses. These signals are processed in the picture-in-picture processorfor the various full screen modes such as zoom, freeze and channel scan.During the channel scan mode, for example, the horizontal and verticalsync present from the video signals input section will have manydiscontinuities because the signals sampled (different channels) willhave non-related sync pulses and will be switched at seemingly randommoments in time. Therefore the sample clock (and read/write video RAMclock) is determined by the free running oscillator. For freeze and zoommodes, the sample clock will be locked to incoming video horizontalsync, which in these special cases is the same as the display clockfrequency.

Referring again to FIG. 4, Y, U, V and C₋₋ SYNC (composite sync) outputsfrom the picture-in-picture processor in analog form can be re-encodedinto Y/C components by encode circuit 366, which operates in conjunctionwith a 3.58 MHz oscillator 380. This Y/C₋₋ PIP₋₋ ENC signal may beconnected to a Y/C switch, not shown, which enables the re-encoded Y/Ccomponents to be substituted for the Y/C components of the main signal.From this point on, the PIP encoded Y, U, V and sync signals would bethe basis for horizontal and vertical timing in the rest of the chassis.This mode of operation is appropriate for implementing a zoom mode forthe PIP, based upon operation of the interpolator and FIFO's in the mainsignal path.

In a multichannel mode, for example that shown in FIG. 1(i), twelvechannels of a predetermined scan list can be displayed in twelve smallpictures simultaneously. The picture-in-picture processor has aninternal clock responsive to a 3.58 MHz oscillator 348. The incomingauxiliary signal is converted from analog to digital form, andresponsive to the chosen special effect, is loaded into a video RAM 350.In the embodiments in the Technical Training Manual described above, thecompiled special effect is converted back to analog form in thepicture-in-picture processor prior to combination with main signal videodata. However, in the wide screen televisions described herein, and duein part to limitations on the number of different clock frequencieswhich are feasible, the auxiliary data is a direct output from the videoRAM 350, without further processing by the picture-in-picture processor320. Minimizing the number of clock signals advantageously reduces radiofrequency interference in the circuitry of the televisions.

With further reference to FIG. 5, the picture-in-picture processor 320comprises analog to digital converting section 322, input section 324,fast switch FSW and bus control section 326, timing and control section328 and digital to analog converting section 330. In general, thepicture-in-picture processor 320 digitizes the video signal intoluminance (Y) and color difference signals (U, V), subsampling andstoring the results in a 1 megabit video RAM 350 as explained above. Thevideo RAM 350 associated with the picture-in-picture processor 320 has amemory capacity of 1 megabit, which is not large enough to store a fullfield of video data with 8-bit samples. Increased memory capacity tendsto be expensive and can require more complex management circuitry. Thesmaller number of bits per sample in the auxiliary channel represents areduction in quantization resolution, or bandwidth, relative to the mainsignal, which is processed with 8-bit samples throughout. This effectivereduction of bandwidth is not usually a problem when the auxiliarydisplayed picture is relatively small, but can be troublesome if theauxiliary displayed picture is larger, for example the same size as themain displayed picture. Resolution processing circuit 370 canselectively implement one or more schemes for enhancing the quantizationresolution or effective bandwidth of the auxiliary video data. A numberof data reduction and data restoration schemes have been developed,including for example, paired pixel compression and dithering anddedithering. A dedithering circuit would be operatively disposeddownstream of the video RAM 350, for example in the auxiliary signalpath of the gate array, as explained in more detail below. Moreover,different dithering and dedithering sequences involving differentnumbers of bits and different paired pixel compressions involvingdifferent number of bits are contemplated. One of a number of particulardata reduction and restoration schemes can be selected by the WSP μP inorder to maximize resolution of the displayed video for each particularkind of picture display format.

The luminance and color difference signals are stored in an 8:1:1six-bit Y, U, V fashion. In other words, each component is quantizedinto six-bit samples. There are eight luminance samples for every pairof color difference samples. The picture-in-picture processor 320 isoperated in a mode whereby incoming video data is sampled with a 640f_(H) clock rate locked to the incoming auxiliary vide synchronizingsignal instead. In this mode, data stored in the video RAM isorthogonally sampled. When the data is read out of thepicture-in-picture processor video RAM 350, it is read using the same640 f_(H) clock locked to the incoming auxiliary video signal. However,even though this data was orthogonally sampled and stored, and can beread out orthogonally, it cannot be displayed orthogonally directly fromthe video RAM 350, due to the asynchronous nature of the main andauxiliary video sources. The main and auxiliary video sources might beexpected to be synchronous only in that instance where they aredisplaying signals from the same video source.

Further processing is required in order to synchronize the auxiliarychannel, that is the output of data from the video RAM 350, to the mainchannel. With reference again to FIG. 4, two four bit latches 352A and352B are used to recombine the 8-bit data blocks from the video RAM4-bit output port. The four bit latches also reduce the data clock ratefrom 1280 f_(H) to 640 f_(H).

Generally, the video display and deflection system is synchronized withthe main video signal. The main video signal must be speeded up, asexplained above, to fill the wide screen display. The auxiliary videosignal must be vertically synchronized with the first video signal andthe video display. The auxiliary video signal can be delayed by afraction of a field period in a field memory, and then expanded in aline memory. Synchronization of the auxiliary video data with main videodata is accomplished by utilizing the video RAM 350 as a field memoryand a first in first out (FIFO) line memory device 354 for expanding thesignal. The size of FIFO 354 is 2048×8. The size of FIFO is related tothe minimum line storage capacity thought to be reasonably necessary toavoid read/write pointer collisions. Read/write pointer collisions occurwhen old data is read out of the FIFO before new data has an opportunityto be written into the FIFO. Read/write pointer collisions also occurwhen new data overwrites the memory before the old data has anopportunity to be read out of the FIFO.

The 8-bit DATA₋₋ PIP data blocks from video RAM 350 are written into2048×8 FIFO 354 with the same picture-in-picture processor 640 f_(H)clock which was used to sample the video data, that is, the 640 f_(H)clock which is locked to the auxiliary signal, rather than the mainsignal. The FIFO 354 is read using the display clock of 1024 f_(H),which is locked to horizontal synchronizing component of the main videochannel. The use of a multiple line memory (FIFO) which has independentread and write port clocks enables data which was orthogonally sampledat a first rate to be displayed orthogonally at a second rate. Theasynchronous nature of the read and write clocks, however, does requirethat steps be undertaken to avoid read/write pointer collisions.

The gate array 300 is common to both wide screen processors 30 and 31.The main signal path 304, auxiliary signal path 306 and output signalpath 312 are shown in block diagram form in FIG. 6. The gate array alsocomprises a clocks/sync circuit 320 and a WSP μP decoder 310. Data andaddress output lines of the WSP μP decoder 310, identified as WSP DATA,are supplied to each of the main circuits and paths identified above, aswell as to the picture-in-picture processor 320 and resolutionprocessing circuit 370. It will be appreciated that whether or notcertain circuits are, or are not, defined as being part of the gatearray is largely a matter of convenience for facilitating explanation ofthe inventive arrangements.

The gate array is responsible for expanding, compressing and croppingvideo data of the main video channel, as and if necessary, to implementdifferent picture display formats. The luminance component Y₋₋ MN isstored in a first in first out (FIFO) line memory 356 for a length oftime depending on the nature of the interpolation of the luminancecomponent. The combined chrominance components U/V₋₋ MN are stored inFIFO 358. Auxiliary signal luminance and chrominance components Y₋₋ PIP,U₋₋ PIP and V₋₋ PIP are developed by demultiplexer 355. The luminancecomponent undergoes resolution processing, as desired, in circuit 357,and is expanded as necessary by interpolator 359, generating signal Y₋₋AUX as an output.

In some instances, the auxiliary display will be as large as the mainsignal display, as shown for example in FIG. 1(d). The memorylimitations associated with the picture-in-picture processor and videoRAM 350 can provide an insufficient number of data points, or pixels forfilling such a large display area. In those circumstances, resolutionprocessing circuit 357 can be used to restore pixels to the auxiliaryvideo signal to replace those lost during data compression, orreduction. The resolution processing may correspond to the resolutionprocessing undertaken by circuit 370 shown in FIG. 4. As an example,circuit 370 may be a dithering circuit and circuit 357 may be adedithering circuit.

The auxiliary video input data is sampled at a 640 f_(H) rate and storedin video RAM 350. The auxiliary data is read out of video RAM 350 isdesignated VRAM₋₋ OUT. The PIP circuit 301 also has the capability ofreducing the auxiliary picture by equal integer factors horizontally andvertically, as well as asymmetrically. With further reference to FIG.10, the auxiliary channel data is buffered and synchronized to the mainchannel digital video by the 4 bit latches 352A and 352B, the auxiliaryFIFO 354, timing circuit 369 and synchronization circuit 368. The VRAM₋₋OUT data is sorted into Y (luminance), U, V (color components), andFSW₋₋ DAT (fast switch data) by demultiplexer 355. The FSW₋₋ DATindicates which field type was written into the video RAM. The PIP₋₋ FSWsignal is received directly from the PIP circuit and applied to theoutput control circuit 321 to determine which field read out of videoRAM is to be displayed during the small picture modes.

The auxiliary channel is sampled at 640 f_(H) rate while the mainchannel is sampled at a 1024 f_(H) rate. The auxiliary channel FIFO 354converts the data from the auxiliary channel sample rate to the mainchannel clock rate. In this process, the video signal undergoes an 8/5(1024/640) compression. This is more than the 4/3 compression necessaryto correctly display the auxiliary channel signal. Therefore, theauxiliary channel must be expanded by the interpolator 359 to correctlydisplay a 4×3 small picture. The interpolator 359 is controlled byinterpolator control circuit 371, which is itself responsive to WSP μP340. The amount of interpolator expansion required is 5/6. The expansionfactor X is determined as follows:

    X=(640/1024)*(4/3)=5/6

The chrominance components U₋₋ PIP and V₋₋ PIP are delayed by circuit367 for a length of time depending on the nature of the interpolation ofthe luminance component, generating signals U₋₋ AUX and V₋₋ AUX asoutputs. The respective Y, U and V components of the main and auxiliarysignals are combined in respective multiplexers 315, 317 and 319 in theoutput signal path 312, by controlling the read enable signals of theFIFO's 354, 356 and 358. The multiplexers 315, 317 and 319 areresponsive to output multiplexer control circuit 321. Output multiplexercontrol circuit 321 is responsive to the clock signal CLK, the start ofline signal SOL, the H₋₋ COUNT signal, the vertical blanking resetsignal and the output of the fast switch from the picture-in-pictureprocessor and WSP μP 340. The multiplexed luminance and chrominancecomponents Y₋₋ MX, U₋₋ MX and V₋₋ MX are supplied to respectivedigital/analog converters 360, 362 and 364 respectively. The digital toanalog converters are followed by low pass filters 361, 363 and 365respectively, shown in FIG. 4. The various functions of thepicture-in-picture processor, the gate array and the data reductioncircuit are controlled by WSP μP 340. The WSP μP 340 is responsive tothe TV μP 216, being connected thereto by a serial bus. The serial busmay be a four wire bus as shown, having lines for data, clock signals,enable signals and reset signals. The WSP μP 340 communicates with thedifferent circuits of the gate array through a WSP μP decoder 310.

In one case, it is necessary to compress the 4×3 NTSC video by a factorof 4/3 to avoid aspect ratio distortion of the displayed picture. In theother case, the video can be expanded to perform horizontal zoomingoperations usually accompanied by vertical zooming. Horizontal zoomoperations up to 33% can be accomplished by reducing compressions toless than 4/3. A sample interpolator is used to recalculate the incomingvideo to a new pixel positions because the luminance video bandwidth, upto 5.5 MHz for S-VHS format, occupies a large percentage of the Nyquistfold over frequency, which is 8 MHz for a 1024 f_(H) clock.

As shown in FIG. 6, the luminance data Y₋₋ MN is routed through aninterpolator 337 in the main signal path 304 which recalculates samplevalues based on the compression or the expansion of the video. Thefunction of the switches or route selectors 323 and 331 is to reversethe topology of the main signal path 304 with respect to the relativepositions of the FIFO 356 and the interpolator 337. In particular, theseswitches select whether the interpolator 337 precedes the FIFO 356, asrequired for compression, or whether the FIFO 356 precedes theinterpolator 337, as required for expansion. The switches 323 and 331are responsive to a route control circuit 335, which is itselfresponsive to the WSP μP 340. It will be remembered that during smallpicture modes the auxiliary video signal is compressed for storage inthe video RAM 350, and only expansion is necessary for practicalpurposes. Accordingly, no comparable switching is required in theauxiliary signal path.

The main signal path is shown in more detail in FIG. 9. The switch 323is implemented by two multiplexers 325 and 327. Switch 331 isimplemented by multiplexer 333. The three multiplexers are responsive tothe route control circuit 335, which is itself responsive to the WSP μP340. A horizontal timing/synchronization circuit 339 generates timingsignals controlling the writing and reading of the FIFOs, as well aslatches 347 and 351, and multiplexer 353. The clock signal CLK and startof line signal SOL are generated by the clocks/sync circuit 320. Ananalog to digital conversion control circuit 369 is responsive to Y₋₋MN. the WSP μP 340 and the most significant bit of UV₋₋ MN.

An interpolator control circuit 349 generates intermediate pixelposition values (K), interpolator compensation filter weighting (C) andclock gating information CGY for the luminance and CGUV for the colorcomponents. It is the clock gating information which pauses (decimates)or repeats the FIFO data to allow samples not to be written on someclocks for effecting compression or some samples to be read multipletimes for expansion.

It is possible to perform video compressions and expansions through theuse of a FIFO. For example, a WR₋₋ EN₋₋ MN₋₋ Y signal enables data to bewritten into the FIFO 356. Every fourth sample can be inhibited frombeing written into the FIFO. This constitutes a 4/3 compression. It isthe function of the interpolator 337 to recalculate the luminancesamples being written into the FIFO so that the data read out of theFIFO is smooth, rather than jagged. Expansions may be performed inexactly the opposite manner as compressions. In the case of compressionsthe write enable signal has clock gating information attached to it inthe form of inhibit pulses. For expanding data, the clock gatinginformation is applied to the read enable signal. This will pause thedata as it is being read from the FIFO 356. In this case it is thefunction of the interpolator 337, which follows the FIFO 356 during thisprocess, to recalculate the sampled data from jagged to smooth. In theexpansion case the data must pause while being read from the FIFO 356and while being clocked into the interpolator 337. This is differentfrom the compression case where the data is continuously clocked throughthe interpolator 337. For both cases, compression and expansion, theclock gating operations can easily be performed in a synchronous manner,that is, events can occur based on the rising edges of the system clock1024 f_(H).

There are a number of advantages in this topology for luminanceinterpolation. The clock gating operations, namely data decimation anddata repetition, may be performed in a synchronous manner. If aswitchable video data topology were not used to interchange thepositions of the interpolator and FIFO, the read or write clocks wouldneed to be double clocked to pause or repeat the data. The term doubleclocked means that two data points must be written into the FIFO in asingle clock cycle or read from the FIFO during a single clock cycle.The resulting circuitry cannot be made to operate synchronously with thesystem clock, since the writing or reading clock frequency must be twiceas high as the system clock frequency. Moreover, the switchable topologyrequires only one interpolator and one FIFO to perform both compressionsand expansions. If the video switching arrangement described herein werenot used, the double clocking situation can be avoided only by using twoFIFO's to accomplish the functionality of both compression andexpansion. One FIFO for expansions would need to be placed in front ofthe interpolator and one FIFO for compressions would need to be placedafter the interpolator.

Interpolation of the auxiliary signal takes place in the auxiliarysignal path 306. The PIP circuit 301 manipulates a 6 bit Y, U, V, 8:1:1field memory, video RAM 350, to store incoming video data. The video RAM350 holds two fields of video data in a plurality of memory locations.Each memory location holds eight bits of data. In each 8-bit locationthere is one 6-bit Y (luminance) sample (sampled at 640 f_(H)) and 2other bits. These two other bits hold either fast switch data (FSW₋₋DAT) or part of a U or V sample (sampled at 80 f_(H)). The FSW₋₋ DATvalues indicate which type of field was written into video RAM. Sincethere are two fields of data stored in the video RAM 350, and the entirevideo RAM 350 is read during the display period, both fields are readduring the display scan. The PIP circuit 301 will determine which fieldwill be read out of the memory to be displayed through the use of thefast switch data. The PIP circuit always reads the opposite field typethat is being written to overcome a motion tear problem. If the fieldtype being read is the opposite type than that being displayed, then theeven field stored in the video RAM is inverted by deleting the top lineof the field when the field is read out of memory. The result is thatthe small picture maintains correct interlace without a motion tear.

The clocks/sync circuit 320 generates read, write and enable signalsneeded for operating FIFOs 354, 356 and 358. The FIFOs for the main andauxiliary channels are enabled for writing data into storage for thoseportions of each video line which is required for subsequent display.Data is written from one of the main or auxiliary channels, but notboth, as necessary to combine data from each source on the same videoline or lines of the display. The FIFO 354 of the auxiliary channel iswritten synchronously with the auxiliary video signal, but is read outof memory synchronously with the main video signal. The main videosignal components are read into the FIFOs 356 and 358 synchronously withthe main video signal, and are read out of memory synchronously with themain video. How often the read function is switched back and forthbetween the main and auxiliary channels is a function of the particularspecial effect chosen.

Generation of different special effects such as cropped side-by-sidepictures are accomplished through manipulating the read and write enablecontrol signals for the line memory FIFOs. The process for this displayformat is illustrated in FIGS. 7 and 8. In the case of croppedside-by-side displayed pictures, the write enable control signal (WR₋₋EN₋₋ AX) for 2048×8 FIFO 354 of the auxiliary channel is active for(1/2)*(5/12)=5/12 or approximately 41% of the display active line period(post speed up), or 67% of the auxiliary channel active line period (prespeed up), as shown in FIG. 7. This corresponds to approximately 33%cropping (approximately 67% active picture) and the interpolatorexpansion of the signal by 5/6. In the main video channel, shown in theupper part of FIG. 8, the write enable control signal (WR₋₋ EN₋₋ MN₋₋ Y)for the 910×8 FIFOs 356 and 358 is active for (1/2)*(4/3)=0.67 or 67% ofthe display active line period. This corresponds to approximately 33%cropping and a compression ratio of 4/3 being performed on the mainchannel video by the 910×8 FIFOs.

In each of the FIFOs, the video data is buffered to be read out at aparticular point in time. The active region of time where the data maybe read out from each FIFO is determined by the display format chosen.In the example of the side-by-side cropped mode shown, the main channelvideo is being displayed on the left hand half of the display and theauxiliary channel video is displayed on the right hand half of thedisplay. The arbitrary video portions of the waveforms are different forthe main and auxiliary channels as illustrated. The read enable controlsignal (RD₋₋ EN₋₋ MN) of the main channel 910×8 FIFOs is active for 50%of the display active line period of the display beginning with thestart of active video, immediately following the video back porch. Theauxiliary channel read enable control signal (RD₋₋ EN₋₋ AX) is activefor the other 50% of the display active line period beginning with thefalling edge of the RD₋₋ EN₋₋ MN signal and ending with the beginning ofthe main channel video front porch. It may be noted that write enablecontrol signals are synchronous with their respective FIFO input data(main or auxiliary) while the read enable control signals aresynchronous with the main channel video.

The display format shown in FIG. 1(d) is particularly desirable as itenables two nearly full field pictures to displayed in a side by sideformat. The display is particularly effective and appropriate for a wideformat display ratio display, for example 16×9. Most NTSC signals arerepresented in a 4×3 format. which of course corresponds to 12×9. Two4×3 format display ratio NTSC pictures may be presented on the same 16×9format display ratio display, either by cropping the pictures by 33% orsqueezing the pictures by 33%, and introducing aspect ratio distortion.Depending on user preference, the ratio of picture cropping to aspectratio distortion may be set any where in between the limits of 0% and33%. As an example, two side by side pictures may be presented as 16.7%squeezed and 16.7% cropped.

The operation can be described in terms of general ratios of speedup andcropping. The video display means can be considered to have a displayformat ratio of width to height of M:N, the first video signal sourcecan be considered to have a display format ratio of A:B and the secondvideo signal source can be considered to have a display format ratio ofC:D. The first video signal can be selectively speeded up by a factor ina first range of approximately 1 to (M/N÷A/B) and selectively croppedhorizontally by a factor in a second range of approximately 0 to[(M/N÷A/B)-1]. The second video signal can be selectively speeded up bya factor in a third range of approximately 1 to (M/N÷C/D) andselectively cropped horizontally by a factor in a fourth range ofapproximately 0 to [(M/N÷C/D)-1].

The horizontal display time for a 16×9 format display ratio display isthe same as a 4×3 format display ratio display, because both have 62.5microsecond nominal line length. Accordingly, an NTSC video signal mustbe sped up by a factor of 4/3 to preserve a correct aspect ratio,without distortion. The 4/3 factor is calculated as ratio of the twodisplay formats:

    4/3=(16/9)/(4/3)

Variable interpolators are utilized in accordance with aspects of thisinvention to speed up the video signals. In the past, FIFOs havingdifferent clock rates at the inputs and outputs have been used toperform a similar function. By way of comparison, if two NTSC 4×3 formatdisplay ratio signals are displayed on a single 4×3 format display ratiodisplay, each picture must be distorted or cropped, or some combinationthereof, by 50%. A speed up comparable to that needed for a wide screenapplication is unnecessary.

Data reduction or compression, and data restoration or expansion, can beaccomplished by alternative methods, in accordance with variousinventive arrangements. In accordance with one alternative, theauxiliary signal is "dithered" by a resolution processing circuit 370and "dedithered" by resolution processing circuit 357. Resolutionprocessing circuit 370 may also be thought of as a data reductioncircuit and resolution processing circuit 357 may also be thought of asa data restoration circuit. Dithering is a process wherein an n-bitsignal has an m-bit dithered sequence added thereto, after which the mleast significant bits are truncated. A 1-bit dithering circuit andcorresponding 1-bit dedithering circuit are shown in FIGS. 15 and 16respectively. A 2-bit dithering circuit and corresponding 2-bitdedithering circuit are shown in FIGS. 17 and 18 respectively.

With reference to FIGS. 15 and 16, a summing circuit 372 combines ann-bit signal with a 1-bit dither sequence. An advantageous 1-bit dithersequence is 01010101, etc. After adding the dither sequence to the 1-bitsignal, the least significant bit is truncated by circuit 374. The n-1bit dithered signal is then processed by pix-in-pix module 320, latches352A and 352B and FIFO 354. The subsequent output of the pip decodingcircuit 306B is an n-1 bit dithered signal. In data restoration circuit357 the n-1 bit dithered signal is supplied to a summing circuit 802 andone input of an AND gate 804. A signal on the other input of AND gate804 masks the least significant bit of the dithered signal. The outputof AND gate 804 is supplied directly to one input of exclusive OR gate801 and is delayed by one clock, or one pixel, by circuit 806, beforebeing supplied as the other input to exclusive OR gate 808. The outputof exclusive OR gate 808 is one input to AND gate 810 and the input to Yinterpolator 359, the input forming the new least significant bit of thededithered signal. The other input of AND gate 810 is a signal havingthe same dither sequence and the same phase as the dithering signalapplied to summing junction 372. The output AND gate 810 is asubtractive input to summing circuit 802. The output of summing circuit802 is combined with the additional bit supplied by the output ofexclusive OR gate 808, providing an n-bit, dedithered signal as an inputto Y interpolator 359.

With reference to FIG. 17, a 2-bit dithering circuit 370' comprises asumming circuit 376, which combines and n-bit signal with a 2-bit dithersequence. In accordance with an inventive arrangement, the dither signalcan be defined by any repetitive sequence of the numbers 0, 1, 2, 3 inany order within the sequence. This definition includes the followingsequences, as listed in Table 1.

                  TABLE 1                                                         ______________________________________                                        0123    1023           2013   3012                                            0132    1032           2031   3021                                            0213    1230           2103   3120                                            0231    1203           2130   3102                                            0312    1302           2301   3201                                            0321    1320           2310   3210                                            ______________________________________                                    

A 2-bit dither sequence which is particularly advantageous is 02130213,etc., which is illustrated in FIG. 17. The n-bit signal which is theoutput of summing circuit 376 has its two least significant bitstruncated by circuit 378. The n-2 bit dithered signal is then processedby pix-in-pix processor 320, latches 352A and 352B, FIFO 354 and pipdecoding circuit 306B.

It appears that the quarter-frequency component is usually moreobjectionable than the half-frequency component, even though thequarter-frequency component has half the amplitude of the half-frequencycomponent. Accordingly, a dedithering scheme can be chosen to suppressonly the quarter-frequency component. A first signal path of thededithering circuit is for delay and amplitude matching. A second signalpath includes a combination inverted bandpass filter and limiter. Theinverted bandpass filter cancels the frequency at the center of thepassband when added to the delay and amplitude matched original signal.The limiter assures that only amplitudes of dither size will becancelled. This dedithering arrangement has no effect upon the halfsample frequency component of the dithered signal. The half-frequencysignal component is low enough in amplitude and high enough in frequencyto have sufficiently low visibility to avoid causing a problem.

Such a dedithering circuit 306D' is shown in FIG. 18. The n-2 bit signalat the output of pip decoding circuit 306B is supplied as an input to atwo clock, or two pixel, delay circuit 822, a two clock, or two pixel,delay circuit 814 and a summing circuit 812. The output of delay circuit814 is a subtractive input to summing circuit 812, the output of whichis an n-1 bit signal. The n-1 bit dithered signal is an input to limitcircuit 816. Output values of the limit circuit are in this caseconfined to [-1, 0, 1,], that is the absolute value of one. The outputof limiting circuit 816 is a 2-bit signal, supplied as an input to twoclock, or two pixel, delay circuit 818 and a subtractive input tosumming circuit 820. Delay circuit 818 and summing circuit 820 form abandpass filter having a gain of two at the center frequency, which is1/4 of the sample rate. The 2-bit signal is a twos complement signal.The output of summing circuit 820 is a 3-bit signal, which is asubtractive input to summing circuit 826. The n-2 bit output of delaycircuit of 822 is an input to multiplier 824. The output of multiplier824 is an n-bit signal, wherein the two least significant bits are equalto 0. The values for the two least significant bits (and somecorrection) are supplied by the summation in circuit 826. The output ofsumming circuit 826 is an n-bit partially dedithered signal, which is aninput to Y interpolator 359.

The resolution, or perceived quality, of the dedithered video signal canbe improved under some circumstances by skewing the dither sequence. Thedither sequence, whether a one or two bit sequence, repeats continuouslyon a given line but is phase shifted on different lines. Many possibleskewing schemes are possible. Two skewing sequences can be particularlyadvantageous in hiding artifacts in the display due to the ditheringprocess itself. These skewing sequences are shown in FIG. 19. The oneand two pixel, field to field skews are those in which all the lines ofone field have the same phase and all the lines of the next field areskewed one or two pixels with respect to the first field. The field tofield skews on 2-bit dithered signals work best for frozen pictures.Some line structure can be visible during live video, where there areflat areas in motion. The one pixel skew is particularly advantageousfor 2-bit dithers if the signal will be dedithered, but the two pixelskew is presently preferred if the signal will not be dedithered.Whether or not the signal should be dedithered depends upon the displayformat.

An alternative to dithering for data reduction is paired pixelcompression, which will be explained with reference to FIG. 20. A fieldis depicted at the top of FIG. 20, the field including lines 1, 2, 3,etc. The pixels of each line are represented by letters. Each pixeldenoted "P" will be retained, whereas each pixel denoted "R" will bereplaced. The permanent and replaced pixels are skewed by one pixel fromline to line. In other words, in the odd number lines, the replacedpixels are the second, fourth, sixth, etc. In the even number lines, thereplaced pixels are the first, third, fifth, etc. The two primaryalternatives are to substitute for each replaced pixel either a 1 bitcode or a 2 bit code. The bits for the codes are taken from the numberof bits available for defining the permanent pixels. The number of bitsavailable for defining the pixels is limited by the storage capacity ofthe video processor. In this case, the CPIP chip and the video RAM 350impose a limit of an average of 4 bits per pixel. If a 1-bit code issubstituted for each replaced pixel, then 7 bits are available for eachpermanent pixel. Similarly, if a 2-bit code is substituted for eachreplaced pixel, then 6 bits are available to describe each permanentpixel. In either event, each pair of successive pixels (one permanentand one replaced) requires a total of 8 bits. A total of 8 bits per pairis an average of only 4 bits per pixel. The data reduction is in therange of 6:4 to 7:4. The replacement sequence is illustrated in aportion of the field including three successive lines: n-1, n, n+1.Pixels to be replaced are designated R1, R2, R3, R4, and R5. Pixels toremain are designated A, B, C and D.

In accordance with a 1-bit coding scheme, a zero will be substituted fora replacement pixel if it is closer in value to the pixel above it thanit is closer in value to the average of the pixels on each side. For theexample in FIG. 20, the 1-bit replacement code for pixel R3 will be zeroif the value of pixel R3 is closer to the value of the average of pixelsB and C than to the value of pixel A. Otherwise, the 1-bit replacementcode will be 1. When the data is reconstructed, pixel R3' will be equalin value to the average of the values of pixels B and C if the 1-bitcode is 0. If the 1-bit code is equal to 1, then the value of pixel R3'will be the same as the value of pixel A.

A replacement and reconstruction sequence for a 2-bit code is alsoillustrated. For pixel R3, the 2-bit replacement code is equal to 0 ifthe value of R3 is closest in value to the value of pixel A. The 2-bitreplacement code is equal to 1 if the value of R3 is closest in value tothe average of values A and B. The 2-bit replacement code is equal to 2fi the value of R3 is closest in value to the average of values A and C.The 2-bit replacement code is equal to 3 if the value of R3 is closestin value to the average of values B and C. The reconstruction sequencefollows the replacement sequence. If the 2 bit code is 0, the value ofpixel R3' is equal to the value of A. If the 2-bit code is equal to 1,the value of pixel R3' is equal to the average of the values of A and B.If the 2-bit code is equal to 2, the value of pixel R3' is equal to theaverage of the values of pixels A and C. If the 2-bit code is equal to3, then the value of pixel R3' is equal to the average of the values ofpixels B and C.

A 1-bit code is advantageous insofar as the permanent pixels aredescribed with 1 bit more resolution. The 2-bit code is advantageous inthat the replaced pixels are described with more resolution. Basingcalculations on the values of only two lines, that is for example, n-1and n, or n and n+1, is advantageous in minimizing the necessary linestorage capacity. On the other hand, a more accurate replacementsequence might be generated if the value D is included in thecalculations, but at the cost of requiring an additional line of videostorage capacity. Paired pixel compression can be particularly effectivefor providing good horizontal and vertical resolution; in some cases,better than dithering and dedithering. On the other hand, the resolutionof diagonal transitions is generally not as good as dithering anddedithering.

In accordance with an inventive arrangement, a number of data reductionand data restoration schemes will be available, including for examplepaired pixel compression and dithering and dedithering. Moreover,different dithering sequences involving different numbers of bits anddifferent paired pixel compressions involving different number of bitswill also be available. The particular data reduction and restorationscheme can be selected by the WSP μP in order to maximize resolution ofthe displayed video for each particular kind of video display format.

What is claimed is:
 1. A signal processing system, comprising:adithering circuit, having: means for combining a dither signal and ann-bit video signal of digital samples; and, means for truncating theleast significant bits of each said sample; and, a dedithering circuit,having: means for delay and amplitude matching defining a first of twoparallel signal paths for said dithered, truncated video signal;bandpass amplifying and limiting means defining a second of said twopaths for said dithered, truncated video signal; and, means for addingoutputs of said two paths to generate an at least partially deditheredn-bit video signal.
 2. The system of claim 1, wherein said dither signalis any repetitive sequence of the numbers 0, 2, 1,
 3. 3. The system ofclaim 1, wherein said truncating means truncates the one leastsignificant bit from each said sample and said output of said second ofsaid two paths supplies a new least significant bit for said at leastpartially dedithered video signal.
 4. The system of claim 1, whereinsaid truncating means truncates at least two least significant bits fromeach said sample and said first of said two paths further comprisesmeans for generating at least two new least significant bits havingvalues determined by said output of said second of said two paths.
 5. Asignal processing system, comprising:a dithering circuit, having: meansfor combining a dither signal with an n-bit video signal of digitalsamples; and, means for truncating the least significant bits of eachsaid sample; and, a dedithering circuit, having: a first of two parallelsignal paths for said dithered, truncated video signal defined by delayand amplitude matching means; a second of said two paths for saiddithered, truncated video signal defined by bandpass filtering meanstuned to a frequency characteristic of said dither signal and bylimiting means; and, means for adding outputs of said two paths togenerate an at least partially dedithered n-bit video signal.
 6. Thesystem of claim 5, wherein said dither signal has a responsecharacteristic defined by at least one frequency component and saidbandpass filtering means is tuned to said at least one frequencycomponent.
 7. The system of claim 5, wherein said dither signal has aresponse characteristic defined by at least two frequency componentshaving relatively higher and lower frequencies and said bandpassfiltering means is tuned to said lower of said at least two frequencycomponents.
 8. The system of claim 5, wherein said dither signal has aresponse characteristic defined by a quarter-sampling-frequencycomponent and a half-sampling-frequency component and said bandpassfiltering means is tuned to said quarter-sampling-frequency component.9. The system of claim 5, wherein said bandpass filtering means in saidsecond of said two paths comprises inverted bandpass filtering means.10. The system of claim 5, wherein said second of said two pathscomprises two bandpass filters and a limiter disposed between said twobandpass filters.
 11. A dithering and dedithering system,comprising:means for adding a dither signal to an n-bit video signal ofdigital samples; means for truncating the least significant bits of eachsaid sample; means for propagating said dithered, truncated videosignal; a first signal path for said propagated video signal defined bydelay and amplitude matching means; a second signal path for saidpropagated video signal defined by bandpass filtering means and limitingmeans; and, means for adding outputs of said first and second signalpaths to generate an at least partially dedithered n-bit video signal.12. The system of claim 11, wherein said dither signal has a responsecharacteristic defined by at least one frequency component and saidbandpass filtering means is tuned to said at least one frequencycomponent.
 13. The system of claim 11, wherein said dither signal has aresponse characteristic defined by at least two frequency componentshaving relatively higher and lower frequencies and said bandpassfiltering means is tuned to said lower of said at least two frequencycomponents.
 14. The system of claim 11, wherein said bandpass filteringmeans in said second signal path comprises inverted bandpass filteringmeans.
 15. The system of claim 11, wherein said second signal pathcomprises two bandpass filters and a limiter disposed between said twobandpass filters.
 16. The system of claim 11, wherein said means forpropagating said dithered, truncated video signal has a transmissioncapacity less than n bits.
 17. The system of claim 11, wherein saidtruncating means truncates the one least significant bit from each saidsample and said output of said second signal path supplies a new leastsignificant bit for said at least partially dedithered video signal. 18.The system of claim 11, wherein said truncating means truncates at leasttwo least significant bits from each said sample and said first signalpath further comprises means for generating at least two new leastsignificant bits having values determined by said output of said secondsignal path.